Selective modification of clock pulses

ABSTRACT

A circuit for modifying a clock pulse train is described. The circuit has an input for receiving the clock pulse train, a first logic circuit having an output which is responsive to a clock pulse edge of a first polarity and a second logic circuit having an output which is responsive to a clock pulse edge of a second polarity. A two input multiplexer is provided to receive respectively the outputs of the first and second logic circuits and is arranged to provide an output representing a modification of the input clock pulse train.

TECHNICAL FIELD

[0001] The present invention relates to a circuit for modifying a clockpulse train, and more particularly but not exclusively to such a circuitin which a clock pulse train can be selectively supplied and, ifsupplied can be selectively inverted.

BACKGROUND TO THE INVENTION

[0002] It is a known requirement to provide a gated clock pulse trainwhich can be inverted or not according to user requirements. A knowncircuit receiving a clock pulse train and operable to either provide noclock, a true clock or an inverted clock has a disadvantage of differentpropagation times through the circuit depending on whether the clock isinverted or not. Known circuits also may present problems such asglitches when switching between inverting and non-inverting clocks.

[0003] It is accordingly an object of the present invention to at leastpartially mitigate the difficulties of the prior art.

SUMMARY OF THE INVENTION

[0004] According to the present invention there is provided a circuitfor modifying a clock pulse train, the circuit comprising a input forsaid clock pulse train, a first logic circuit having an output which isresponsive to a clock pulse edge of a first polarity, a second logiccircuit having an output which is responsive to a clock pulse edge of asecond polarity opposite to said first polarity and a two-inputmultiplexer having a control input coupled to receive said clock pulsetrain, the first input of the multiplexer receiving the output of thefirst logic and the second input of the multiplexer receiving the outputof the second logic circuit.

[0005] Preferably the first logic circuit comprises a first latchcircuit having an input and said second logic circuit comprises a secondlatch circuit having an input, the circuit further comprising a controlinput terminal connected to said input of said first latch and to saidinput of said second latch via respective paths, the propagation delaydifference between said path being less than the period of a clockpulse.

[0006] According to a second aspect of the present invention there isprovided a circuit for selectively modifying a clock pulse train, thecircuit comprising an input for said clock pulse train, a first clockedlatch having an input, an output and a clock terminal, a second clockedlatch having an input, an output and a clock terminal, and a two inputmultiplexer having a control input connected to receive said clock pulsetrain, the first input of the multiplexer being connected to the outputof the first latch and the second input of the multiplexer beingconnected to the output of the second latch, said input for said clockpulse train being connected to the clock input terminals of said firstand second latches wherein the first latch is responsive to a risingedge in said clock pulse train and the second latch is responsive to afalling edge in said clock pulse train.

[0007] Preferably the circuit comprises a control input and an enableinput, and first logic circuitry connecting said control input and saidenable input to the input of said first latch and second logic circuitryconnecting said control input and said enable input to the input of saidsecond latch.

[0008] Conveniently said logic circuitry comprises a two input AND gatereceiving said control input and enable input at its two inputs and saidfirst logic circuitry comprises a two input AND gate receiving at itstwo inputs said enable input and the inverse of the said control input.

[0009] An embodiment of the present invention will be described by wayof example only with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010]FIG. 1 shows a schematic diagram of a clock gating circuitaccording to the prior art;

[0011]FIG. 2 shows an embodiment of a circuit for selectively invertinga clock pulse train in accordance with the present invention; and

[0012]FIG. 3 shows a timing diagram useful in understanding theembodiment of FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

[0013] In the Figures like reference numerals refer to like parts.

[0014] Referring first to FIG. 1, a prior art circuit comprises atwo-input multiplexer 10 having a first input 11, a second input 12 andan output 13. The first input 11 is directly connected to a clock node20 and the clock node 20 is connected to the second input 12 via aninverter 14. The multiplexer 10 has a control terminal 15 which isconnected to a control node 21. The output 13 of the multiplexer 10 isconnected to an output terminal 40 via a two-input AND gate 16, whoseother input is connected to the output of a latch 17. The input of thelatch 17 is provided at an enable input 22 and the latch is clocked at aclock node 18 by the output of the multiplexer 13.

[0015] To explain the operation, consider first the situation where thecontrol input is at logic 1. In this case, the first input 11 to themultiplexer is connected directly to the output 13 of the multiplexer.Thus, the clock pulse train incident at the clock pulse node 20 appearsdirectly at the output 13 of the multiplexer.

[0016] In the alternative situation, when the control node is at logiczero, the multiplexer connects its second input 12 to its output 13.From inspection of the circuit it will be seen that the clock pulsetrain appears at the second input terminal 12 after passing through theinverter 14 and thus the second multiplexer input receives an invertedversion of the clock for output from the output terminal 13 of themultiplexer 10.

[0017] It will however be appreciated by those skilled in the art thatthere is a propagation delay difference between the two paths for thetrue and inverse clock. This is due to the delay caused by the inverter14. Equally, in the known circuit, it is quite hard to change clockorientation. For example to change over it is necessary to ensure theinput at enable input 22 is de-asserted, then wait for the end of theclock cycle before altering the state of control input 21 to avoidglitches.

[0018] The output 13 of the multiplexer 10 is, as has previously beennoted, provided to one input of the two-input AND gate 16, and also tothe clock input of latch 17. Further reference to FIG. 1 shows that thelatch 17 is transparent while the clock input is low and latches whilethe clock input is high. Thus, while the enable input 22 is at a lowlevel, the input to the latch 17 is low and the output of the latch 17remains permanently low thereby causing the output terminal 40 to beconstantly at logic zero. When the enable input 22 is high then theoutput of the latch 17 is permanently high so that the output 40 changesstate with changes at the state at the output 13 of the multiplexer 10after the gate delay of the AND gate 16. If the enable input 22 changesstate during a positive going half cycle of the clock input at terminal18 of the latch 17, then the clock pulse at output 40 will eithercontinue (if previously enabled) until the end of the instant clockpulse or will not be enabled (if previously disabled) until the end ofthe clock pulse at output 13.

[0019] It will be noted that changes of state at enable input 22 onlytake effect while the clock terminal 18 is at a low level and thus donot provide any effect until the next high state of the clock at node13.

[0020] Turning now to FIG. 2, an embodiment of a clock pulsemodification circuit 2 consists of a two-input multiplexer 100 having afirst input 101, a second input 102, a select input 103 and an outputconnected to a circuit output 104. The circuit has a clock terminal 110connected in use to receive a clock pulse train and the clock terminalis connected to the select input 103 of the two-input multiplexer 100.The first input 101 of the two-input multiplexer 100 is supplied fromthe output of a first latch 120 and the second input 102 is suppliedfrom the output of a second latch 130. The circuit 2 has a control input111 and an enable input 112, together with a reset input 113. The secondlatch 130 has an input 131 which is provided by the output of a firsttwo-input AND gate 140 which is connected with a first input to theenable input terminal 112 and its second input to the control input 111.The input 121 of the first latch 120 is provided by the output of atwo-input gating circuit 150 which receives at a first input the controlinput 111 and at a second input the enable input 112. The gating circuit150 provides an AND function of the inverse of the control input 111 andthe true enable input 112. The first latch 120 has a clock input node122 connected to the clock terminal 110 and the second latch 130 has aclock node 132 likewise connected to the clock terminal 110. However,the first latch 120 responds to positive-going edges of clock pulses atthe clock terminal 110 whereas the second latch 130 responds to thenegative-going edges of clock pulses at clock terminal 110.

[0021] The reset input 113 via an inverter 160, is connected to a ‘cleardata’ input of first latch 120. This ensures that when the clock isdisabled a known output at circuit output 104 is present. In theembodiment, when the clock input is low, the first latch 120 is offwhich means that mode 101 would be at an unknown value at power-up.Adding reset input (at high after power-up) means that 101 starts at aknown (zero) level.

[0022] It would alternatively be possible to connect the output of theinverter 160 to a ‘set data’ input of the second latch 130 to ensurestarting at logic 1. Other start arrangements will be clear to thoseskilled in the art.

[0023] Turning now to FIG. 3, the operation of the circuit will now bedescribed.

[0024] The top waveform shows the clock pulses at the clock terminal110, which is shown here as having a unity mark-two-space ratio. Thesecond tray shows the control input 111 which starts at logic 1 beforefalling to logic zero at time T1. The enable input 112 is the thirdwaveform which starts at logic one and falls to logic zero at time T4.The fourth waveform is the input 121 to the first latch 120 whichchanges substantially at the same instant as the change of the controlinput 111 but instead changes from logic zero to logic one atsubstantially time T1. It will be recalled that the first latch respondsto the rising edge of the clock pulse train and thus the output 101(fifth waveform) of the first latch does not change state to logic 1until time T2, around a quarter of a clock cycle later than time T1,when the clock pulse 110 has a rising edge. The sixth waveform shows theinput 131 to the second latch. This input substantially follows thecontrol input 111 but, as it will be recalled that the second latch 130responds to the falling edge of the clock waveform the output 102(seventh waveform) of the latch remains at logic one until time T3around three quarters of a clock period after T1, at the next fallingedge of the clock.

[0025] At time T4 the enable input 112 falls to the logic zero disablestate and this change of state does not appear at the output 101 of thefirst latch 120 until time T5, around three quarters of a clock periodlater, at the next rising clock edge.

[0026] The last waveform on FIG. 3 shows the clock pulse output atterminal 104. Operation of the multiplexer causes the output to bederived from sequential segments of the two inputs, 101, 102 to themultiplexer. Until time T3, the first input 101 to the multiplexer is atlogic zero and the second input 102 to the multiplexer is at logic one.However, at time T1 the input to the first latch changes state and atthe next rising edge T2 the latch output changes state to logic one sothat sufficient time is available for the latch output to settle beforeone half clock period later, at time T3 the multiplexer switches betweenlogic one from the second input 102 to logic one from the first input101. Thereafter, it will be seen that the clock pulse is inverted untiltime T5 when the enable input causes both latches to have logic zerooutputs. Once again, it will be seen that the transition in the enableinput gives sufficient time for the latch output to stabilize at logiczero before that logic zero is passed by the multiplexer.

[0027] A fundamental feature of this embodiment is that because themultiplexer is controlled by the clock state, and the latches respond toclock edges, the multiplexer always connects a stable input to theoutput. The unselected input receives a possibly changing level, butthis is not passed through to the output.

[0028] Changes can be made to the invention in light of the abovedetailed description. In general, in the following claims, the termsused should not be construed to limit the invention to the specificembodiments disclosed in the specification and the claims, but should beconstrued to include all methods and devices that are in accordance withthe claims. Accordingly, the invention is not limited by the disclosure,but instead its scope is to be determined by the following claims.

What is claimed is:
 1. A circuit for modifying a clock pulse train, thecircuit comprising: an input for said clock pulse train; a first logiccircuit having an output which is responsive to a first clock pulse edgeof the clock pulse train, the first clock pulse edge having a firstpolarity; a second logic circuit having an output which is responsive toa second clock pulse edge of the clock pulse train, the second clockpulse edge having a second polarity opposite to said first polarity; anda two-input multiplexer having an output as an output of said circuit, acontrol input coupled to receive said clock pulse train, a first inputreceiving the output of the first logic circuit, and a second inputreceiving the output of the second logic circuit.
 2. The circuit ofclaim 1 wherein the first logic circuit comprises a first latch circuithaving an input and said second logic circuit comprises a second latchcircuit having an input, the circuit further comprising a control inputterminal connected to said input of said first latch and to said inputof said second latch via respective paths having a propagation delaydifference that is less than a period of the clock pulse train.
 3. Thecircuit of claim 1 wherein the multiplexer is connected to the first andsecond logic circuits such that the output of one of the logic circuitschanges only while the multiplexer connects the output of the otherlogic circuit as said circuit output.
 4. A circuit for selectivelymodifying a clock pulse train, the circuit comprising: an input for saidclock pulse train; a clocked first latch having an input, an output anda clock terminal; a clocked second latch having an input, an output anda clock terminal; and a two input multiplexer having a control inputconnected to receive said clock pulse train, a first input connected tothe output of the first latch, and a second input connected to theoutput of the second latch, said input for said clock pulse train beingconnected to the clock terminals of said first and second latcheswherein the first latch is responsive to a rising edge in said clockpulse train and the second latch is responsive to a falling edge in saidclock pulse train.
 5. The circuit of claim 4, further comprising acontrol input, an enable input, first logic circuitry connecting saidcontrol input and said enable input to the input of said first latch,and second logic circuitry connecting said control input and said enableinput to the input of said second latch.
 6. The circuit of claim 5wherein said second logic circuitry comprises a two input AND gatereceiving said control input and enable input at its two inputs and saidfirst logic circuitry comprises a two input AND gate receiving at itstwo inputs said enable input and the inverse of said control input. 7.The circuit of claim 6 having a start input for causing said circuitoutput to be at a predetermined level when the clock pulse train is notprovided.
 8. The circuit of claim 7 wherein said first latch has a resetinput responsive to said start input, whereby the output of said firstlatch is set to a predetermined logic level during start-up.
 9. A methodof selectively modifying a clock pulse train, the method comprising:receiving the clock pulse train at respective inputs of first and secondlogic circuits having respective outputs; selectively enabling the firstlogic circuit with a first enable signal, thereby causing the firstlogic circuit, when enabled, to output a first portion of the clockpulse train; selectively enabling the second logic circuit with a secondenable signal, thereby causing the second logic circuit, when enabled,to invert a second portion of the clock pulse train and output theinverted second portion; and alternately electrically connecting to anoutput terminal either the output of the first logic circuit or theoutput of the second logic circuit depending on a logic level of theclock pulse train.
 10. The method of claim 9, further comprising causingthe first logic circuit to output a signal at a predetermined logiclevel in response to a reset signal.
 11. The method of claim 9 whereinthe first and second logic circuits are latches.
 12. The method of claim9 wherein the first enable signal enables the first logic circuit if afirst control signal is at a first logic level and a second controlsignal is at a second logic level and the second enable signal enablesthe second logic circuit if both of the first and second control signalsare at the second logic level.
 13. The method of claim 9 wherein thealternately electrically connecting step is performed by a multiplexerhaving a first input coupled to the output of the first logic circuit, asecond input coupled to the output of the second logic circuit, anoutput coupled to the output terminal, and a control input coupled tothe clock pulse train.